The invention pertains to the clock signal generator circuit implemented with FET devices. More particularly, the invention pertains to such a clock generating circuit in which an output clock signal having high (1) and low (0) levels corresponding to positive and negative power supply levels is produced from an input clock signal having high and low levels corresponding to the positive power supply level and the ground level. The circuit of the invention finds application as a clock signal generator for devices such as an CCD (Charge Coupled Device), particularly, as a circuit for generating a clock signal used for clocking a data signal from the last bit position of the CCD to a utilization circuit.
A prior art clock generator circuit of the same general type to which the invention pertains is shown in FIG. 1. In this circuit, the input clock signal .phi..sub.1 is applied to an input inverter circuit composed of FET devices 11-14. The channels of the devices 12 and 14 are connected in series between a power supply terminal to which a positive potential V.sub.DD is applied and ground. The source and the drain of the device 13 are interconnected to form a capacitor in a well known manner. The capacitor (device) 13 is connected as a bootstrap capacitor between node A (the gate of the device 12) and node B (the source of the device 12). The input clock signal drives the gate of the device 14.
The inverted input signal from the input circuit from the drain of the device 14 at node B is applied to the gate of a device 16, the channel of which is connected in series with that of a device 15 between V.sub.DD and ground. The input signal .phi..sub.1 is also applied to the gate of the device 15. Thus, the devices 15 and 16 form a second inverting stage with an uninverted but delayed version of the input signal being developed at a node C. A third circuit composed of devices 17-20, identical in arrangement to the circuit of the devices 11-14, re-inverts the signal developed at the node C. Thus, an inverted version of the input signal .phi..sub.1 is developed at a node E with a delay between the signal developed at the node E and the input clock signal .phi..sub.1 of a duration determined by parameters of the devices 11-20.
An output section is composed of devices 21-24 in a driver stage and devices 25 and 26 in an output stage. The sources of the devices 24 and 26 are connected to the substrate potential V.sub.SX (which is a negative voltage), while the drains of the devices 22 and 25 are connected to the positive power supply potential V.sub.DD. As an example, it is assumed that V.sub.DD =8.5 V and V.sub.SX =-2.2 V. The device 23 is connected as a bootstrap capacitor between a node G at the interconnection point between the drain of the device 24 and the source of the device 22 and a node F at the gates of the devices 22 and 25 and the source of the device 21. The transistor 21 has a gate connected to the power supply potential V.sub.DD, and the input signal .phi..sub.1 is applied to the source.
Operationally, when .phi..sub.1 =0 (ground level), the node E is at the positive power supply potential V.sub.DD, and hence the devices 24 and 26 are turned on while the devices 22 and 25 are turned off. The output signal .phi..sub.1 ' is thus driven to near the substrate potential V.sub.SX. At this time, the node G is of course also at a potential near the substrate potential V.sub.SX and the node F near ground potential. When .phi..sub.1 changes from the 0 to the 1 state, a potential near V.sub.DD is applied to the node F almost immediately through the device 21. Because the node G is then still near V.sub.SX, the bootstrap capacitor 13 is thus rapidly charged through the device 24. After the predetermined delay time, the voltage at node E goes to ground. Accordingly, the devices 24 and 26 are shut off (partially) to thereby release the nodes G and H. The potential developed across the capacitor 23 is then applied as a bootstrap drive signal to the gates of the devices 22 and 25, thereby driving the output signal .phi..sub.1 to the positive power supply potential V.sub.DD.
Although this circuit is in fact capable of producing the desired output waveform, nevertheless, it is disadvantageous for two reasons.
First, the power dissipation of the circuit is quite high. The reason for this is that when .phi..sub.1 =1, all of the devices 11, 12, 14, 17, 18 and 20 are turned on, while when .phi..sub.1 =0, the devices 15 and 16 are turned on. This provides current paths directly through those devices between V.sub.DD and ground. Also, there is some power loss in the devices 22-26 since when .phi..sub.1 =1, the gates of the devices 24 and 26 are at ground while the sources are at V.sub.SX (below ground), and hence the devices 24 and 26 are partially turned on. Current can thus flow from V.sub.DD to ground through the devices.
Secondly, in order to keep the devices 24 and 26 turned on when .phi..sub.1 =1 and the potential of the node E is near ground, because the sources of the devices are below ground, it is necessary to increase the threshold voltages of the devices 24 and 26. To do this, it has been the practice to utilize a second polysilicon layer in the fabrication of the gate structures of the devices that includes a barrier implant. The use of such a layer, however, is disadvantageous in that fabrication of the circuit becomes more difficult. Moreover, if the amount of the barrier implant is not within precisely determined limits, the circuit may be inoperative.